1. Field of the Invention
This invention relates to a data storage system, and particularly to a system of efficiently using memory storage areas as replacements for defective areas in a digital memory.
2. Prior Art
Very large data storage systems typically employ a number of identical memory or storage elements which are combined into an overall memory system. A number of basic storage modules (BSM) are arrayed each having its own address bus and data bus coupling the BSM memory to a memory controller. Each BSM includes in addition to a number of memory array devices, buffers, terminators, and ancillary timing and control functions. The manufacture of memory array devices per se is characterized by high rates of rejection, that is, components that are not initially perfect. The mass production of information storage devices having a large number of semi-conductor memory cells integrated onto a single chip is therefore still the subject of low yield rates since, if any one of the memory cells is rendered inoperative, the entire array which includes that inoperative memory cell is also rendered inoperative. Yield rates at the present level of technology in the manufacture of integrated circuit elements with initially perfect devices remains less than 50%. Attempts to increase the yield rate have been frustrated by the continued growth in the number of cells on each chip with the attendant probability of defects increasing as the number of elements in the circuit similarly increases.
Given cost factors, techniques to use imperfect memories have been proposed as a means to increase yield rates. That is, attempts have been made to utilize memory systems having defective components. A typical prior art approach is to employ so-called "discretionary" wiring which involves individual wiring around bad memory locations. While this technique allows defective memory modules to be utilized, it introduces additional aspects of expense and further production problems. The technique requires extensive fault testing and labor.
Reference is made to U.S. Pat. Nos. 3,644,902; 3,714,637; 3,765,001; and 3,781,826 relating to a method of using a partially good memory. The scheme increases effective yield but sacrifices usable bits which exist in quadrants or octants containing bad cells and requires more chips than all-good BSM's. The technique also requires additional space, power and cooling and introduces design and manufacturing complexities. Furthermore there is no known method of applying this approach to recovering from faults which develop after the BSM has been assembled.
Other techniques also recognize that memories with defective storage locations may be utilized, for example, by simply skipping those portions of the memory (See: IBM Technical Disclosure Bulletin, Vol. 20, p. 1841, (1977)) or by the replacement of defective memory locations with spare locations from a second, dedicated, redundant memory region (See: IBM Technical Disclosure Bulletin, Vol. 12, p. 1441 (1970)). The use of dedicated redundant regions may also occur in substitute memory locations of the main memory (See: U.S. Pat. No. 4,051,460).
In other prior art systems, a recognition exists that undedicated memory locations of the main memory may be used as a replacement for faulty memory modules. The substitute module can, for example, be selected as a replacement because of its low use in the overall system operation. In U.S. Pat. No. 4,150,428, the designation of a memory module as a substitute memory occurs prior to detection of faults in other memory modules. The substitute memory module is then loaded with data substantially identical to that of the faulty module after a fault has been detected. Examples of substitute modules of low priority are, for example, those having high addresses in a read/write operation or scratch-pad memory areas.
U.S. Pat. No. 3,633,175 shows a defect tolerant memory having a main memory portion and an auxiliary memory portion. A content addressable memory (CAM) is provided for storing the address of defective locations in the main memory. Additionally, the addresses in the auxiliary memory containing defect free data are stored. Hence, during a read operation, before the data in the system's memory address register is delivered to an address decoder and driver for the operation of the main memory, the CAM compares the address to be accessed with addresses of defective main memory locations which it has stored therein. Should the comparison yield an address of an address stored in the CAM, it then delivers an auxiliary address to the address decoder driver to direct the information exchange to the spare address location that has been assigned. As a result, a defect-tolerant memory system is defined wherein the use of the CAM renders the operation of the system "transparent" to the use of two memories.
In that regard, U.S. Pat. No. 3,633,175 recognizes that the main memory M1 and the auxiliary memory M2 can either be portions of a memory M, or can be constructed as physically separated entities, that is, on separate integrated circuit chips or separate magnetic memory structures. However, irrespective of the location of the two memories, the '175 patent dedicates two areas with the auxiliary memory being reserved to contain data which has been previously stored in defective locations in the main memory.
Accordingly, while the prior art has recognized the use of partially good components in constructing memory systems, in each case the system architecture is predisposed to a design philosophy requiring either inordinately large memory units or separate dedicated memory modules as reserve blocks. The design criteria in those systems utilizing spare locations or specific reserve blocks thereby still is dictated by a formal requirement of at least a partially perfect portion of the memory. While partially defective components may be utilized, the resulting system tends to be larger than required and therefore relatively inefficient.
It is therefore an object of this invention to provide a system of facilitating the use of memories having defective locations without increasing the overall size of the memory.
It is another object of this invention to provide a memory that is designed and implemented as if all components were perfect.
Yet another object of this invention is to provide a defect tolerant memory that operates without loss of efficiency when defects are encountered during normal use.
A further object of this invention is to provide a defect tolerant memory system that is more economical in production yield rates than conventional memory systems.